The top is defined in HDL source file TopCpld.vhd.
This regmap has readablestrobes="true", so all strobe bits are readable by default. This attribute should only be used for older regmaps to maintain compatibility with previous versions of XmlParse. New regmaps should either use the 'clearable' attribute or should explicitly define readable bits in the same bit position as the strobe bits.
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Initial Value not specified
This register is defined in HDL source file TopCpld.vhd.
Bits | Name |
15..0 |
Represents the product family name/number. This field reads back as 0xCAFE. |
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Initial Value not specified
This register is defined in HDL source file TopCpld.vhd.
Bits | Name |
15..0 |
Contains minor revision code (0,1,2,...). |
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Initial Value not specified
This register is defined in HDL source file TopCpld.vhd.
Bits | Name |
15..0 |
Contains major revision code. |
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Initial Value not specified
This register is defined in HDL source file TopCpld.vhd.
Bits | Name |
15..8 |
Contains build code day code. |
7..0 |
Contains build code hour code. |
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Initial Value not specified
This register is defined in HDL source file TopCpld.vhd.
Bits | Name |
15..8 |
Contains build code revision year code. |
7..0 |
Contains build code month code. |
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Initial Value not specified
This register is defined in HDL source file TopCpld.vhd.
Bits | Name |
15..0 |
Contains scratch value for testing. The state of this register has no effect on any other operation in the CPLD. |
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Initial Value not specified
This register is defined in HDL source file TopCpld.vhd.
Bits | Name |
15..8 |
Reserved |
7..1 |
Reserved |
0w |
Asserting this bit resets all the CPLD logic. This reset will return all registers on the PS SPI interface to their default state! To use this reset correctly, first write CpldReset to '1', then write it to '0'. Registers will be reset on the _falling_ edge of CpldReset. |
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Initial Value not specified
This register is defined in HDL source file TopCpld.vhd.
Bits | Name |
15..8 |
Reserved |
7..5 |
Reserved |
4 |
Setting this bit to '0' will allow the Phase DAC to exclusively control the VCXO voltage. Defaults to '1', which allows the Phase DAC to adjust the voltage (but the LMK still has control as well). |
3..0 |
Reserved |
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Initial Value not specified
This register is defined in HDL source file TopCpld.vhd.
Bits | Name |
15..8 |
Reserved |
7..5 |
Reserved |
4 |
Live lock detect status from the TX LO. |
3..1 |
Reserved |
0 |
Live lock detect status from the RX LO. |
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Initial Value not specified
This register is defined in HDL source file TopCpld.vhd.
Bits | Name |
15..8 |
Reserved |
7..1 |
Reserved |
0 |
Drives the Mykonos hard reset line. Defaults to de-asserted. Write a '1' to assert the reset, and a '0' to de-assert. |
Value | Name |
0 | |
1 | |
2 | |
3 |
This enumerated type is defined in HDL source file TopCpld.vhd.
Value | Name |
0 | |
1 | |
2 | |
3 |
This enumerated type is defined in HDL source file TopCpld.vhd.
Value | Name |
0 | |
1 | |
2 | |
4 | |
5 | |
6 | |
7 |
This enumerated type is defined in HDL source file TopCpld.vhd.
Value | Name |
1 | |
2 | |
4 |
This enumerated type is defined in HDL source file TopCpld.vhd.
Value | Name |
1 | |
2 | |
4 | |
8 |
This enumerated type is defined in HDL source file TopCpld.vhd.
Value | Name |
1 | |
2 | |
4 |
This enumerated type is defined in HDL source file TopCpld.vhd.
Value | Name |
0 | |
1 | |
2 | |
3 |
This enumerated type is defined in HDL source file TopCpld.vhd.
Value | Name |
0 | |
1 | |
2 | |
3 |
This enumerated type is defined in HDL source file TopCpld.vhd.
Value | Name |
1 | |
2 | |
4 | |
8 |
This enumerated type is defined in HDL source file TopCpld.vhd.
Value | Name |
0 | |
1 |
This enumerated type is defined in HDL source file TopCpld.vhd.
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Initial Value not specified
This register is defined in HDL source file TopCpld.vhd.
Bits | Name |
15..0 |
Contains scratch value for testing. The state of this register has no effect on any other operation in the CPLD. |
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Initial Value not specified
This register is defined in HDL source file TopCpld.vhd.
Bits | Name |
15..8 |
Reserved |
7..1 |
Reserved |
0w |
Asserting this bit resets all the CPLD logic on the PL SPI interface. This reset will return all registers to their default state! To use this reset correctly, first write PlCpldReset to '1', then write it to '0'. Registers will be reset on the _falling_ edge of PlCpldReset. |
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Initial Value not specified
This register is defined in HDL source file TopCpld.vhd.
Bits | Name |
15 |
Reserved |
14 |
Drives the Mykonos input port TX1_ENABLE. |
13 |
Red/Green combo LED for the TRX channel. |
12..11 |
TRX switch control. The values for this bitfield are in the TrxSwitch table. (show here) |
10 |
Write a '1' to enable the TX path PA in between TX switches 2 and 3. |
9 |
Write a '1' to enable the TX path Amp in between TX switches 3 and 4. The path (from Mykonos) is: TxSw4 -> Amp -> DSA -> TxSw3. |
8 |
Write a '1' to enable the lowband mixer. Note that Ch1TxLowbandMixerPathSelect must be properly configured to select the mixer path. |
7 |
Controls Switches 4 and 5. Write a '1' to select the Lowband Mixer path. Writing '0' will select the bypass path around the mixer. Default is '0'. Note: Individual control over these switches was removed as an optimization to allow all TX controls to fit in one 16 bit register. |
6 |
Controls Switch 3. Bypasses the filter bank and PA, or doesn't. The values for this bitfield are in the TxSwitch3 table. (show here) |
5..2 |
Controls Switch 2. Filter bank distribution switch. The values for this bitfield are in the TxSwitch2 table. (show here) |
1..0 |
Controls Switch 1. Filter bank receive switch. The values for this bitfield are in the TxSwitch1 table. (show here) |
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Initial Value not specified
This register is defined in HDL source file TopCpld.vhd.
Bits | Name |
15..14 |
Reserved |
13..10 |
Controls Switch 5. Lower filter bank receive switch. The values for this bitfield are in the Rx1Switch5 table. (show here) |
9..7 |
Controls Switch 4. Upper filter bank receive switch. The values for this bitfield are in the Rx1Switch4 table. (show here) |
6..4 |
Controls Switch 3. Lower filter bank transmit switch. The values for this bitfield are in the Rx1Switch3 table. (show here) |
3..2 |
Controls Switch 2. First filter switch. Selects between bypass path and the upper/lower filter banks. The values for this bitfield are in the Rx1Switch2 table. (show here) |
1..0 |
Controls Switch 1. Selects between the cal, bypass, RX2, and TRX paths. The values for this bitfield are in the Rx1Switch1 table. (show here) |
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Initial Value not specified
This register is defined in HDL source file TopCpld.vhd.
Bits | Name |
15..11 |
Reserved |
10 |
Drives the Mykonos input port RX1_ENABLE. |
9 |
Red/Green combo LED for the TRX channel. |
8 |
Green LED for RX2 channel. |
7 |
Write a '1' to enable the RX path LNA2 between RxSw5 and RxSw6. |
6 |
Write a '1' to enable the RX path LNA1 between RxSw4 and RxSw6. |
5 |
Write a '1' to enable the RX path Amp directly before the Mykonos inputs. |
4 |
Write a '1' to enable the lowband mixer. Note that Ch1RxLowbandMixerPathSelect must be properly configured to select the mixer path. |
3 |
Controls Switches 7 and 8. Write a '1' to select the Lowband Mixer path. Writing '0' will select the bypass path around the mixer. Default is '0'. Note: Individual control over these switches was removed as an optimization to allow all TX controls to fit in one 16 bit register... so the same was done for the RX path for continuity. |
2..0 |
Controls Switch 6. Selects between the upper and lower filter banks and bypass path. The values for this bitfield are in the Rx1Switch6 table. (show here) |
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Initial Value not specified
This register is defined in HDL source file TopCpld.vhd.
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Initial Value not specified
This register is defined in HDL source file TopCpld.vhd.
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Initial Value not specified
This register is defined in HDL source file TopCpld.vhd.
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Initial Value not specified
This register is defined in HDL source file TopCpld.vhd.
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Initial Value not specified
This register is defined in HDL source file TopCpld.vhd.
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Initial Value not specified
This register is defined in HDL source file TopCpld.vhd.
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Initial Value not specified
This register is defined in HDL source file TopCpld.vhd.
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Initial Value not specified
This register is defined in HDL source file TopCpld.vhd.
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Initial Value not specified
This register is defined in HDL source file TopCpld.vhd.